Frequency divider with reduced jitter and transmitter based thereon

ABSTRACT

Apparatus ( 50 ) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK 1 , fvco). The apparatus ( 50 ) comprises a chain of frequency dividing cells ( 51 - 56 ), wherein each of the frequency dividing cells ( 51 - 56 ) has a definable division ratio (DR) and comprises:—a clock input (CKi) for receiving an input clock (CKin);—a divided clock output (CKi+1) for providing an output clock (CKout) to a subsequent frequency dividing cell;—a mode control input (MDi) for receiving a mode control input signal (MDin) from the subsequent frequency dividing cell; and—a mode control output for providing a mode control output signal (MDout) to a preceding frequency dividing cell. The apparatus ( 50 ) further comprises a logic network ( 58 ) having m inputs. Each of the m inputs is connected to a mode control input (MDi, MDi+1, MDi+2) of one of the m consecutive frequency dividing cells ( 51 - 54 ). The output signal (fdiv) is made available at an output ( 59 ) of the logic network ( 58 ), whereby the output signal (fdiv) has a pulse width (( ) that is wider than the widest pulse width of any of the mode control input signals (MDin) at the m inputs of the logic network ( 58 ).

[0001] The present invention concerns frequency dividers and apparatusfor frequency division. More particularly, this invention relates to afrequency divider architecture and circuit technique based on the zipperdivider architecture being well suited for use in transmitters, inparticular for radio frequency signal transmission. Also concerned aretransmitters without modulators.

[0002] Great efforts have been made in radio frequency (RF) designtowards one-chip transceivers in standard complementary metal oxidesemiconductor (CMOS) in recent years. Particularly the CMOSimplementation of frequency dividers and frequency synthesizers —one ofthe key building blocks in a transmitter—have attracted a lot ofattention. The most notable trend here is the zipper dividerarchitecture and the so-called current-mode logic (CML).

[0003] The known zipper divider is comprised of a chain of divide-by-2/3cells of identical circuitry. Shown in FIG. 1 is a conventionaldivide-by-2/3 cell 10 having five terminals 11-15: clock input (CKin)11, divided clock output (CKout) 12, mode control input (MDin) 13, modecontrol output (MDout) 14, and a programming input (P) 15. Eachdivide-by-2/3 cell 10 consists of two circuit blocks: a prescaler logicblock 16 which divides either by 2 or 3, controlled by a swallow signal(SW) generated by another block called end-of-cycle logic 17. When aprogramming bit P=0 (with MDin=1 or MDin=0) is applied at theprogramming input 15, then the cell 10 divides by 2 and when P=1 andMDin=1 it divides by 3.

[0004] The divide-by-2/3 cells are typically implemented in CML. Anelementary CML logic circuit comprises several stacked differentialpairs, two resistive or active loads, and one tail current source.Further details concerning CML implemented zipper dividers is describedby C. Vaucher and Z. Wang in “A low-power truly-modular 1.8 GHzprogrammable divider in standard CMOS technology”, ESSCIRC'99.pp.406⁴⁰⁹, 1999, and by C. Vaucher, I. Ferencic, M. Locher, S.Sedvallson, U. Voegeli, and Z. Wang in “A family of low-power trulymodular programmable dividers in standard 0.35-mm CMOS technology”, IEEEJ. Solid-State Circuits SC-35, No. 7, pp.1039-1045, 2000.

[0005] An example of a known frequency divider 20 comprising a chain ofsix divide-by-2/3 cells 21-26 and an input latch 27 is depicted in FIG.2A. Implemented in CMOS, the divider 20 is capable of operating at aninput clock frequency (CK1) in the GHz range. FIG. 2B shows the terminalsignals of the frequency divider 20. The clock input and clock outputsignals (CK1-CK7) are depicted in the plots on the left hand side ofFIG. 2B and the mode control signals (MD1-MD6) are depicted on the righthand side together with CK1. The amplitudes of the clock input and clockoutput signals (CK1-CK7) range in the present example between −500 mVand +500 mV (peak-to-peak) since the divider 20 is realized in CML. Inthe present example, for most of the time, the cells 21-26 divide theirrespective clock input by 2. If the division ratio is 3, the pulse widthis wider, as visible on the left hand side of FIG. 2B. In case of thesignal CK3, for example, at the times t1 and t2 the division ratio is 3.This is due to the fact that a binary word P=111111 is applied to theprogramming inputs (P0-P5) of the input latch 27. If the programminginputs are always logic “1” the division ratio of the individual cells21-26 is only determined by the mode control signal (MD) issued by asubsequent cell to a preceding cell.

[0006] For low-power applications, a divider architecture capable ofreducing the power consumption by up to 50% has been proposed in theco-pending patent application entitled “Improved frequency divider withreduced power consumption, apparatus based thereon, and method for powerefficient frequency division”. This co-pending patent application wasfiled on 22.12.2000 is currently assigned to the assignee of the presentpatent application. Application number 00128322.5 was assigned.

[0007] A novel reclocking and a novel frequency divider architecturewith double-reclocking are presented in the co-pending patentapplication entitled “Improved frequency divider with reduced jitter andapparatus based thereon”. This co-pending patent application was filedon 17.05.2001 is currently assigned to the assignee of the presentpatent application. Application number 01112125.8 was assigned. Thenovel architecture and technique presented in this patent application isbased on the known zipper divider architecture.

[0008] A modulator 31 has long been an indispensable component of atransmitter 30. It modulates the carrier frequency by the data to betransmitted, as shown in FIG. 3, where the carrier frequency (f0) isgenerated by a phase-locked-loop (PLL) 32.

[0009] By contrast, the state-of-the-art transmitters 40 tend to exploitthe fractional-N PLL transmitter, where a PLL 41 is used not only forthe generation of the carrier frequencies (f0) but also for themodulation. In such transmitters 40, the traditional analog modulator isreplaced by an adder 42 and a sigma/delta (Σ/Δ) modulator 43, asdepicted in FIG. 4. Both are favorably digital.

[0010] The fractional-N divider is the key component in this transmitter40. It comprises a frequency divider 44 with integer division ratio (DR)and the Σ/Δ modulator 43, which controls the DR and randoms the phaseerror. The control data (Pi) of the frequency divider 44 contain theinformation of both the data to be transmitted and the carrier frequency(f0) to control the modulus of the divider 44.

[0011] At GHz range and above, the before mentioned zipper dividerarchitecture and CML technique have proven to be the first choice forlow-power. If the divider 44 is to be implemented in zipper architectureand CML technique, a number of problems will be encountered when thevarious parts of the transmitter 40 of FIG. 4 are being connected. Theseinclude the output pulse width, output jitters, the reference dutycycle, and the timing constraints, etc. Some of the issues are evencontradictory in nature.

[0012] Jitter, for example, is a major concern in frequency divider andtransmitters because introducing even a small jitter into these circuitsleads to dramatic changes in its frequency spectrum and timingproperties, thus resulting in lower signal-to-noise ratio, increased biterror rates, and higher interference to neighboring channels. Jitter isalso important in clocked and sampled data systems because thezero-crossing often contain information so any uncertainties inswitching instants will cause error.

[0013] Until now, the output pulse width and jitter in particular arenot seriously considered when designing zipper divider circuitry in CMLand when designing transmitters employing such zipper dividers.

[0014] It is thus an objective of the present invention to improvecurrent divider circuitry and transmitters.

[0015] It is another objective of the present invention to provide afrequency divider with reduced or eliminated output jitter.

[0016] It is another objective of the present invention to provide afrequency divider with an output pulse width that is wide enough forproperly feeding a phase frequency detector being part of a transmitter,to identify the timing constraints, and to show a simple way to addressthe issue.

[0017] A novel frequency divider architecture with a logic network ispresented herein. The novel architecture and technique is based on theknown zipper divider architecture. It allows to provide an output signalhaving the desired pulse width and low jitter.

[0018] An apparatus, according to the present invention, is claimed inclaim 1.

[0019] Various advantageous embodiments are claimed in claims 2 through9.

[0020] An apparatus according to the present invention is particularlywell suited for use in a transmitter, without the need of a modulator. Atransmitter in accordance with the present invention is claimed in claim10.

[0021] Various advantageous embodiments of the transmitter are claimedin claims 11 through 16.

[0022] The frequency divider architecture provided herein allowsreducing or eliminating jitters of different kinds of circuits, and inparticular asynchronous circuits like the zipper divider circuits.Devices according to the present invention are very effective androbust.

[0023] Various embodiments are proposed herein to achieve the bestperformances.

[0024] The most salient benefits of the embodiments presented hereininclude a comparatively spurious free output spectrum with very lowlevels of phase noise close to the carrier, and considerable reductionof the manufacturing costs.

[0025] The fractional-N PLL transmitters according to the presentinvention are well suited for use in transceivers and other devices.

[0026] Other advantages of the present invention are addressed inconnection with the detailed embodiments.

[0027] For a more complete description of the present invention and forfurther objects and advantages thereof, reference is made to thefollowing description, taken in conjunction with the accompanyingdrawings, in which:

[0028]FIG. 1 is a conventional divide-by-2/3 cell comprising two logicblocks.

[0029]FIG. 2A is a conventional zipper divider architecture comprisingsix divide-by-2/3 cells.

[0030]FIG. 2B is a diagram depicting the clock signals and mode controlsignals of the conventional zipper divider architecture of FIG. 2A.

[0031]FIG. 3 is a schematic representation of a conventionaltransmitter/transceiver that comprises a modulator.

[0032]FIG. 4 is a schematic representation of a popular fractional-N PLLtransmitter.

[0033]FIG. 5 is a schematic representation of a frequency divider withOR-gate, in accordance with the present invention.

[0034]FIG. 6 is a diagram depicting the signals of the frequency dividerof FIG. 5.

[0035]FIG. 7 is a schematic representation of a fractional-N PLLtransmitter, according to the present invention, comprising a frequencydivider with OR-gate.

[0036]FIG. 8 is a diagram depicting the signals of the zipper divider ofFIG. 7.

[0037]FIG. 9 is a diagram showing certain waveforms of one embodiment.

[0038]FIG. 10 is a diagram showing possible scenarios of misalignment.

[0039]FIG. 11 is a schematic representation of part of a fractional-NPLL transmitter with a logic network according to the present invention.

[0040]FIG. 12 is a schematic representation of a converter, according tothe present invention.

[0041] For sake of simplicity, certain of the signal lines in thevarious Figs. are shown as single ended signal lines. In reality, manyof the signals are differential, meaning that there are in fact twosignal lines. Other signals may be digital signals that are several bitswide. Where necessary for a better understanding of the invention, thewidth of the digital signal is indicated. The indicated signal width isapplication/embodiment specific.

[0042] The pulse width of a frequency divider's output signal (fdiv) andthe jitter are two contradictory issues. Depending on the circuitry inwhich the frequency divider is employed, the jitter of the output signal(fdiv) and the pulse width is to be considered.

[0043] For a zipper divider any signal among MDi may serve as the outputbecause they all have the same frequency but different pulse width, asclearly seen from FIG. 2B for example. There are also different sizes ofthe associated jitters, which are not visible in the waveforms shown. Asthe pulse width of MDi changes with index i, it is possible to choose aMDi wide enough to meet the requirement. However, for low-power thecurrent consumption is scaled down cell-by-cell, and at the same timethe load resistance is scaled up to maintain the gain of the dividercell. Hence, the wider the pulse width of MDi is, the larger theassociated jitter will be. Furthermore, due to the asynchronous natureof this type of frequency divider, jitters accumulate along the signalpath cell by cell. Therefore, amongst MD1 to MD6, the signal at MD1 hasthe smallest jitter but unfortunately the narrowest pulse width, and thesignal at MD6 has the widest pulse width but the largest jitter. Forthese reasons, wider output pulse width and lower output jitters arecontradictory issues in the design.

[0044] The solution proposed and described herein allows to generate thedesired pulse width with the lowest possible jitter. According to thepresent invention, this is achieved by combining several consecutive MDisignals, including MD1, by an appropriate logic circuit. Preferably, anOR gate is employed as logic circuit.

[0045]FIG. 5 shows a first frequency divider 50, in accordance with thepresent invention. It comprises in the present example six divide-by-2/3cells 51-56 in a chain. The frequency divider 50 generates an outputsignal (fdiv) whose frequency is lower than the frequency of an inputsignal (fvco) being applied to the input (CK1) 57 of the cell 51. Thefrequency dividing cells 51-56 have a pre-defined division ratio (N). Inthe present example the cells are divide-by-2/3 cells, where N=2 or N=3.Each of the cells 51-56 comprises five terminals. Note that in the firstcell 51 of the chain only four of the terminals are used. The firstterminal serves as a clock input for receiving an input clock (CKin);one terminal is a divided clock output for providing an output clock(CKout) to a subsequent frequency dividing cell, one terminal is a modecontrol input for receiving a mode control input signal (MDin) from thesubsequent frequency dividing cell, and another one of the terminals isa mode control output for providing a mode control output signal (MDout)to a preceding frequency dividing cell. In the present example, an inputclock signal fvco is applied to the terminal (CK1) 57 of the first cell51. This input signal fvco is processed in order to generate an outputsignal fdiv having a lower frequency than the input signal fvco.

[0046] According to the present invention, the frequency divider 50further comprises a logic network for combining several of the signalsat the mode control inputs. In the present embodiment, the logic networkcomprises an OR-gate 58 having m inputs (m=4 in the present embodiment).Each of the m inputs is connected to a mode control input MD1, MD2, MD3and MD4 of one of m consecutive frequency dividing cells 51, 52, 53, 54.Several consecutive MDi signals (MD1, MD2, MD3 and MD4), including MD1,are combined by the OR-gate 58. An output signal (fdiv) is madeavailable at an output 59 of the OR-gate 58. The output signal (fdiv) atthe output 59 has a pulse width τ_(1,4) that is wider than the widestpulse width of any of the mode control input signals MD11, MD2, MD3 orMD4 at the m inputs of the OR-gate 58. By ORing the first MD1 to MDisignals of the six-stage zipper divider 50 of FIG. 5, the resultantpulse width τ_(1,4) is wider than any of the OR-gate's m input signals.

[0047] In the upper part of FIG. 6 the MDi signals of the frequencydivider 50 are shown, where i=1,2 . . . 6. At the bottom of FIG. 6, theoutput signal (fdiv) 60 is shown. The pulse width τ_(1,4) of the outputsignal (fdiv) 60 is wider than the width of any of the pulses of thesignals MD1, MD2, MD3 or MD4.

[0048] Another output signal (fdiv) 61 is shown at the bottom of FIG. 6.The pulse width τ_(1,5) of the output signal (fdiv) 61 is wider than thewidth of any of the pulses of the signals MD1, MD2, MD3, MD4 or MD5. Theoutput signal (fdiv) 61 can be obtained by feeding the signals at MD1through MD5 to an OR-gate with five inputs, for example.

[0049] Using an appropriate equation, one can show that with the kind ofarrangement shown in FIG. 6 the resultant pulse width is wider than thepulse width any of the input signals. This finding guides the design offurther embodiments, as will be shown below. One can calculate the pulsewidth of an output signal (fdiv) resulting from any combination of thesignals MDi. FIG. 6 shows two cases, each with different pulse widths:τ_(1,4), τ_(1,5.)

[0050] The width τ_(1,x) of the output signal fdiv depends on thedivision ratio (DR) of the frequency divider. For a n-stage zipperdivider, the available range of its DR are: γ_(min)=2^(n) andγ_(max)=2^(n+1)−1, where γ is the division ratio.

[0051] A transmitter 70, in accordance with the present invention, isillustrated in FIG. 7. In the present example, the transmitter 70 isrealized in CMOS technology. It comprises a first data input 71 for datato be transmitted by the transmitter 70 across a channel 72. A seconddata input 73 is provided. Data applied to this second data input 73enable a carrier frequency (f0) to be selected. The first data input 71and the second data input 73 are fed into adder 74 providing a digitalsignal (herein referred to as modulating data) by adding the data to betransmitted and the data identifying the carrier frequency (f0). In thepresent embodiment, the modulating data are 16 bits wide. They areapplied to an input 75 of a Σ/Δ modulator 76 (also called S/D-modulator)that processes the digital signal to generate a binary code word (Pi)allowing together with mode control input signals (MDin) the actualdivision ratio (N) of a zipper divider 77 to be switched. The zipperdivider 77 allows integer division ratios, which, together with theΣ/Δ-modulator 76, constitutes a fractional-N divider. In the presentembodiment, the binary code word (Pi) is 6 bits wide since the zipperdivider 77 has six divide-by-2/3 cells (not shown in FIG. 7). The zipperdivider 77 is connected to a logic network providing at its output 79 anoutput signal (fdiv). In the present embodiment, the logic networkcomprises an OR-gate 78. The transmitter 70 further comprises a phasefrequency detector (PFD) 80 for processing the output signal (fdiv) anda reference signal (fref). The phase frequency detector (PFD) 80generates an error signal at output 86 based on comparing the inputsignal fref and the PLL feedback signal fdiv.

[0052] In the present embodiment, the phase frequency detector (PFD) 80is followed by a loop filter 81 and a voltage controlled oscillator(VCO) 82. The voltage controlled oscillator (VCO) 82 provides an outputsignal (fvco) at an output 83. The input data at input 75 contain theinformation (input data) of both the signal to be transmitted via acommunication channel 72 and the carrier frequency (f0) to control themodulus of the zipper divider 77. As a result, the output signal fvco atthe output 83 of the voltage-controlled oscillator (VCO) 82 is amodulated radio-frequency (RF) signal at the desired carrier frequency(fo). The transmitter 70 further comprises a power amplifier (PA) 84 andan antenna 85 through which the modulated radio-frequency (RF) signal isemitted into the channel 72. The VCO 82 output signal fvco at output 83is used to generate the PLL feedback signal fdiv. For this purpose, theoutput signal fvco is fed to an input 87 of the zipper divider 77.

[0053] When the reference frequency is kept constant, which is normallythe case, changing γ results in a VCO frequency proportional to y. Itfollows that for i=n the available minimum output pulse width of theoutput signal (fdiv) is approximately equal to 1/0.5 fref, half theperiod of the reference frequency fref, and the attainable maximumoutput pulse width γ=γ_(min) approaches the period of fref.

[0054] When the output signal (fdiv) of the frequency divider 77 is fedto the phase frequency detector (PFD) 80, the PFD 80 needs some time toreact. For proper operation of the PFD 80, its input pulse width at theinput 79 must not be too narrow. On the other hand, output jitter has tobe minimized. When the PFD 80 is edge triggered—which is normally thecase—the jitter at the triggering edge is to be considered. The twoinput signals fref (a stable reference signal) and fdiv of the PFD 80 donot need to have the same duty cycle.

[0055] The above proposed circuit technique to generate wider pulsewidth, for example, the one shown in FIG. 5 with i=4, or the one shownin FIG. 7 with i=5, is very simple and robust, and the output signalfdiv is free of glitches thanks to the overlap between consecutive MDisignals. Since MD1 is included when combining the mode control input(MDi) signals at the OR-gate 78, lowest possible jitter on the failingedges can be obtained if the OR-gate 78 is a low-jitter design.Similarly, modifying the logic network by replacing the OR-gate 78 by aNOR-gate results in lowest possible jitter on the rising edges.

[0056] For proper operation of the frequency dividers in a PLL,according to the present invention, particularly for fractional-Ndivision ratios, it is most important that the frequency divider 77divides correctly under the control of the Σ/Δ modulator 76. As thedivision ratio of the frequency divider 77 is controlled by data Pi, itis absolutely critical to know the timing constraints for the data Pi.

[0057] To avoid a complex and tedious timing analysis, an alternativeapproach is adopted here. For the sake of simplicity and clarity, onemay first consider the simplest case in which the division ratio is aninteger and constant. The result of this analysis is given in FIG. 8.From the design of the zipper divider 77 it can be concluded that forcorrect operation the control bits P0-P5 are only allowed to changeduring time interval Tx, shown in FIG. 8, and they must be stable andkept unchanged during the rest of that output cycle To. Having gainedthe knowledge about the timing of the control bits Pi, one can considernext what timing relationship between Pi and fref/fdiv is required. Asthe PFD 80 is required to sense the phase difference between fref andfdiv on the falling edges for the present embodiment, the falling edgeof fdiv should be the one directly derived from MD 1. This is shown inFIG. 8 by the dashed line 90.

[0058] When the PLL is locked, both input signals fdiv and fref of thePFD 80 will have the same frequency and the same phase, and the fallingedge 91 and 92 of fref and fdiv will be aligned for a constant divisionratio. Because the control data Pi are provided by the Σ/Δ modulator 76and the Σ/Δ modulator 76 is clocked by fref (see FIG. 7), it ispreferred to have the Σ/Δ modulator 76 and other digital circuitsoperating on the rising edges to minimize the noises and disturbances.

[0059] Based on the previous discussion on the timing constraint for Pi,the required location of the rising edge of fref can be deduced, asshown in FIG. 8. Therefore, the minimum duty cycle of fref must belarger than 50%. Quantitatively, one can express the required duty cycleΩ as

Ω=(To−Tx)/To=47/γ.

[0060] The required duty cycle Ω depends on the division ratio γ. Forγ=γ_(min)=64, the duty cycle according to this equation has to be largerthan 73.44%. This situation is shown in FIG. 8.

[0061] Because 50% duty cycle is used in virtually almost allapplications, exotic duty cycles other than 50% have to be avoided, ifpossible. It has be found out that to allow a reference clock fref with50% duty cycle the falling edge 91 of the signal fdiv has to berepositioned somewhere close to the rising edge of MD4. For this reason,the output pulse of fdiv can no longer be generated as proposed above inorder to maintain 50% duty cycle for the reference clock fref, and toclock the control data Pi on the rising edges out of the Σ/Δ modulator76. However, one can derive the falling edge 101 of the signal fdiv fromthe rising edge 102 of MD4, and the rising edge 103 from MD5, asillustrated in FIG. 9, thus yielding an output signal fdiv with a pulsewidth of

τ=τ_(1,5)−τ_(1,4)=24/(fref τ).

[0062] Again, the pulse width is dependent on the division ratio. Theavailable minimum pulse width now is 7.268 ns for fref-26 MHz and themaximum division ratio of 127.

[0063] With the above embodiment, the required minimum pulse width and50% duty cycle for the reference clock fref have all been met.Unfortunately, the benefit of low level of phase noise offered by thefractional-N PLL transmitter 70 is ruined because the signal MD4contains jitter that is too large.

[0064] A circuit to eliminate these jitters has been proposed in theabove-mentioned co-pending patent application entitled “Improvedfrequency divider with reduced jitter and apparatus based thereon”. Acircuit in accordance with this co-pending patent application can becombined with the embodiments presented herein.

[0065] Misalignment is a potential problem between the control bits Piand the divided output cycle of fdiv, leading to a wrong VCO frequencyfvco at the output 83, and more severely, it may even lead to a scenariothat the PLL never be locked. Prior to the locked state, the signalsfref and fdiv have different frequencies and phases. Because the controlbits Pi are clocked out at the rising edges and because of thefractional-N division, it might happen during the acquisition processthat the control bits Pi are misaligned with the output cycle of thesignal fdiv of the zipper divider 77, as illustrated in FIG. 10, leadingto a serious situation in which within one output cycle To twoconsecutive division ratios are accidentally applied to the zipperdivider 77. As a result, within this cycle To the zipper divider 77divides by these two different division ratios: first part by divisionratio i 104 and the rest by division ratio i+1 105.

[0066] Clearly, this should be prevented from happening.

[0067] A simple method to solve this problem with two different divisionratios is to add an n-bit input latch/dFF, and let it be clocked by asignal being synchronized with the divider output fdiv rather than fref.This clocking signal is designated as load signal 106 in FIGS. 9 and 11,derived directly from MD5. Data Di coming from the Σ/Δ modulator 76 areclocked out of the input latch/dFF, here as Pi, on the rising edge ofthe signal load 106.

[0068] For proper operation, the set-up time tsu and hold time of theused input latch/dFF has to be respected. As the proposed solution inFIG. 9 allows 50% duty cycle for fref, the available set-up time isgiven by tsu=(γ/2−24)/(fref γ), which is again division ratio dependent.The minimum available set-up time tsu is obtained when the frequencydivider 77 divides by its minimum division ratio, which is 76 for thisembodiment. For fref=26 MHz one gets 7.1 ns indicating more than enoughmargin. The available hold time is equal to To-tsu, which is so longthat it does not cause any concern.

[0069] The fractional-N division ratio has several implications. In theabove discussions a constant division ratio was assumed. For afractional-N PLL, however, the required division ratio, which is underthe control of the Σ/Δ modulator 76, keeps changing. In worst case thedivision ratio may change once every output cycle To. Because a timinganalysis for all possible division ratio combinations is quite complexand tedious, and even impossible due to the pressure of time-to-market,a detailed analysis is avoided.

[0070] Instead, the following approach has been adopted. First, oneassumes a constant division ratio, as was done above, and tries to makethe initial design to have as much margin as possible. Then, one checksthe designed frequency divider 77 within a PLL under the worst case bysimulation. The frequency divider 77 may cover all possible divisionratios and the division ratio changes once every output cycle. One hasto check and make sure that every cycle the designed frequency dividerindeed divides the set division ratio.

[0071] Another frequency divider 120, according to the presentinvention, is depicted in FIG. 11. This embodiment is based on thetiming diagram of FIG. 9. In the present embodiment, the logic network138 for combining several of the mode control signals MDi comprises aplurality of elements/components. Because in most cases PDF 121 is madeof full-swing logic dFFs, the logic network 138 comprises two converters122, 123 as an interface to convert the small and differential MDisignals into full swing (rail-to-rail) signals. The first converter 123is followed by an inverter 136 to invert the signal at MD5. Furthermore,the logic network 138 comprises a reclocking unit 135 that is clocked bythe signals CK3 and fvco, and an XOR-gate 134. The output signal fdiv isprovided at the output of the NOR-gate 134. The signal fdiv is generatedin a manner that the rising edge 103 of MD5 provides for the rising edge107 of fdiv and the rising edge 102 of MD4 provides for the falling edge101 of fdiv. Further details concerning the reclocking technique appliedin the present embodiment can be found in the co-pending patentapplication entitled “Improved frequency divider with reduced jitter andapparatus based thereon”.

[0072] A simple realization of such a converter 122 is given in FIG. 12.The converter 122 comprises of a one-stage operational amplifier 124followed by two inverters 125 and 126. Because only the jitters ofconverter 122 are critical to the phase noise of this PLL transmitter127, the current consumption of the converter 123 can be reduced,indicated by a smaller sign of a triangle in FIG. 11.

[0073] It must be pointed out that the proposed architecture can beapplied to zipper dividers with any number of cells without exception.

[0074] The present invention is suited for use in communication systemsand other system. The present invention is suited for use intransmitters and receivers. The invention is particularly well suitedfor use in one-chip CMOS transceivers. Systems in accordance with thepresent invention can be employed in cellular phones (GSM or UMTS, forexample), DECT hand sets, personal communication systems, Bluetoothdevices, just to mention a few examples.

[0075] A frequency divider in accordance with the present invention canbe combined with other circuits in order to realize power efficientimplementations of transceivers, radio frequency (RF) integratedcircuits (ICs), GSM solutions, DECT devices, PCS, and Bluetoothsolutions.

[0076] It is appreciated that various features of the invention whichare, for clarity, described in the context of separate embodiments mayalso be provided in combination in a single embodiment. Conversely,various features of the invention which are, for brevity, described inthe context of a single embodiment may also be provided separately or inany suitable subcombination.

[0077] In the drawings and specification there has been set forthpreferred embodiments of the invention and, although specific terms areused, the description thus given uses terminology in a generic anddescriptive sense only and not for purposes of limitation.

1. Apparatus for generating an output signal (fdiv) whose frequency islower than the frequency of an input signal (CK1, fvco), the apparatus(50; 70; 120) comprising: a chain of frequency dividing cells (51-56;128-133), wherein each of the frequency dividing cells (51-56; 128-133)has a definable division ratio (DR) and comprises a clock input (CKi)for receiving an input clock (CKin); a divided clock output (CKi+1) forproviding an output clock (CKout) to a subsequent frequency dividingcell; a mode control input (MDi) for receiving a mode control inputsignal (MDin) from the subsequent frequency dividing cell; and a modecontrol output for providing a mode control output signal (MDout) to apreceding frequency dividing cell; the apparatus (50; 70; 120) furthercomprising a logic network (58; 78; 122, 123, 134, 135, 136, 138) havingm inputs, each of the m inputs being connected to a mode control input(MDi, MDi+1, MDi+2) of one of m consecutive frequency dividing cells(51-54; 131, 132) of the chain of frequency dividing cells (51-56;128-133), the output signal (fdiv) being made available at an output(59; 137) of the logic network (58; 78; 122, 123, 134, 135, 136, 138),whereby the output signal (fdiv) has a pulse width (τ) that is widerthan the widest pulse width of any of the mode control input signals(MDin) at the m inputs of the logic network (58; 78; 122, 123, 134, 135,136, 138).
 2. The apparatus of claim 1, wherein m≧2.
 3. The apparatus ofclaim 1, wherein the logic network comprises an OR-gate (58; 78) or anNOR-gate (134).
 4. The apparatus of claim 1 or 2, wherein the logicnetwork is designed such that the rising edge (103) of a signal at afirst mode control input (MD5) of one of the m consecutive frequencydividing cells (132) triggers the rising edge (107) of the output signal(fdiv), and the rising edge (102) of a signal at a second mode controlinput (MD4) of one of the m consecutive frequency dividing cells (131)triggers the falling edge (101) of the output signal (fdiv).
 5. Theapparatus of claim 1 or 2, wherein the logic network comprisesconverters (122, 123), an inverter (136), a reclocking unit (135) and anNOR-gate (134).
 6. The apparatus of claim 1, wherein the frequencydividing cells are divide-by-2/3 cells, wherein the division ratio (N)can be switched between 2 and
 3. 7. The apparatus of claim 1, comprisinglatches being realized in current-mode logic (CML).
 8. The apparatus ofclaim 1, wherein each frequency dividing cell (51-56; 128-133) of thechain of frequency dividing cells (51-56; 128-133) comprises aprogramming input (P1-P5) for application of a binary code word (Pi)allowing together with the mode control input signals (MDin) thedivision ratio (N) of the frequency dividing cells (51-56; 128-133) tobe switched.
 9. The apparatus of claim 1, wherein the chain of frequencydividing cells (51-56; 128-133) is realized according to the zipperdivider architecture.
 10. Transmitter (70; 127), in particular atransmitter realized in CMOS technology, comprising: a first data input(71) for data to be transmitted by the transmitter (70; 127) across achannel (72), a second data input (73) enabling a carrier frequency (f0)to be provided by applying data determining the carrier frequency (f0),an adder (74) providing modulating data by adding the data to betransmitted and the data determining the carrier frequency (f0), azipper divider (77; 120) with a logic network (78; 138) providing at itsoutput (79; 137) an output signal (fdiv), a Σ/Δ modulator (76; 139)processing the modulating data to generate a binary code word (Pi)allowing together with mode control input signals (MDin) the actualdivision ratio (N) of the zipper divider (77; 120) to be switched, aphase frequency detector (PFD, 80; 121) processing the output signal(fdiv) and a reference signal (fref), a loop filter (81) situated afterthe phase frequency detector (PFD, 80; 121), a voltage controlledoscillator (VCO, 82) subsequent to the loop filter (81), the voltagecontrolled oscillator (VCO, 82) providing an output signal (fvco)defined by the carrier frequency (f0) being frequency modulated with thedata to be transmitted.
 11. The transmitter of claim 10, whereby thezipper divider (77; 120), the logic network (78; 138), the phasefrequency detector (PFD, 82; 121), and the voltage controlled oscillator(VCO, 80) form a phase-locked-loop (PLL).
 12. The transmitter of claim10, whereby the Σ/Δ modulator (76; 139) has an input to which thereference signal (fref) is applied.
 13. The transmitter of one claim 10,whereby the logic network comprises a an OR-gate (78) or an NOR-gate(134).
 14. The transmitter of claim 10, whereby the transmitter is afractional-N PLL-transmitter.
 15. The transmitter of claim 10, wherebythe logic network (78; 138) is designed such that the rising edge (103)of a signal at a first mode control input (MD5) of one of the mconsecutive frequency dividing cells (132) triggers the rising edge(107) of the output signal (fdiv), and the rising edge (102) of a signalat a second mode control input (MD4) of one of the m consecutivefrequency dividing cells (131) triggers the falling edge (101) of theoutput signal (fdiv).